1. Field of the Invention
The present invention relates to a switching apparatus for use, for example, in switching data in asynchronous transport mode (ATM) networks.
2. Description of the Prior Art
FIG. 1 (PRIOR ART) of the accompanying drawings shows a block diagram of conventional switching apparatus 1 for use in an ATM network. In the FIG. 1 apparatus, a plurality of self-routing switch elements (SREs) 2 are connected together in matrix form. Each SRE 2 has four input ports I1 to I4 and four output ports O1 to O4. Within each individual SRE, 2 ATM cells received at any input port I1 to I4 can be routed to any output port O1 to O4, and a routing tag associated with each ATM cell passing through an SRE 2 is used to determine to which output port the cell concerned will be passed. Each output port has an associated first-in-first-out cell buffer having a storage capacity of, for example, 75 cells.
As shown in FIG. 1 (PRIOR ART) the SREs 2 are arranged in a matrix, so that in this example the overall switching apparatus has twelve input ports and 16 output ports. To facilitate such matrix-form connection, each SRE 2 has four regeneration outputs R1 to R4, which are associated respectively with the input ports I1 to I4 of the SRE 2 concerned, and also has four expansion ports E1 to E4 which are associated respectively with the output ports O1 to O4 of the SRE 2 concerned. Cells received at one of the input ports I1 to I4 are regenerated and retimed for output by the associated regeneration output ports R1 to R4. Cells received at one of the expansion ports E1 to E4 are inserted in the cell buffer of the associated output port O1 to O4.
The SREs 2 of the FIG. 1 apparatus are convenient to use in the illustrated matrix form because each SRE provides re-timed active outputs which allow direct connection to the nearest neighboring SREs. This eliminates the need for passive buses and reduces the interconnect problems between adjacent SREs at the printed circuit board level.
The number of switch elements required to form a switch having N input ports by N output ports is proportional to N.sup.2, and hence the matrix configuration is only really appropriate for relatively small switching apparatuses, for example up to 32 input ports by 32 noutput ports. For larger switches, individual matrices 1 of the kind shown in FIG. 1 can be interconnected using a multipath delta arrangement as shown in FIG. 2 (PRIOR ART) of the accompanying drawings.
In FIG. 2 (PRIOR ART), the switching apparatus 5 comprises eight SRE matrices 1 of the kind shown in FIG. 1. Thus, each of the SRE matrices 1 in FIG. 2 contains a plurality of SREs 2 arranged in matrix form. The matrices 1 in FIG. 2 are arranged in two columns, and each matrix in the left-hand column has output ports connected respectively to the input ports of each SRE matrix 1 in the right-hand column, and vice versa.
The SRE matrices employed in the FIGS. 1 and 2 switching apparatuses have fixed bussing arrangements and fixed amounts of memory (typically the cell buffer associated with each output port of an SRE 2 has a storage capacity of 75 cells). Any increase in the size of the switching apparatus results in a square law increase in the number of SREs and also a square-law increase in the volume of "statistics" (i.e. traffic flow information) required to monitor the different switching nodes within the switching apparatus. Such an increase in the volume of statistics inevitably increases the processing demands on the switch controller.
Furthermore, as the number of switching nodes increases, there are more points at which congestion can occur. It is difficult to monitor all of these points simultaneously to assess the traffic flows and establish which source ports are leading to the congestion.
In addition, the cell delay variation (CDV) of an SRE matrix-based switch is proportional to the size of the switch.
A further problem is that the memory capacity of each SRE is fixed at some relatively limited value, and is not expandable to cope with different switch architectures.